Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Subscribe to D&R SoC News Alert
English
Mandarin
Register
Login
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Subscribe to D&R SoC News Alert
Register
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC Days 2021
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
IP-SoC 2021
Browse Wireline Communication
ATM / Utopia (4)
CEI (14)
Cell / Packet (6)
Error Correction/Detection (146)
Ethernet (150)
Fibre Channel (1)
HDLC (6)
Interleaver/Deinterleaver (1)
Modulation/Demodulation (17)
Optical/Telecom (50)
Other (38)
CEI-112G-MR/LR (8)
CEI-112G-VSR (4)
CEI-56G-MR/LR (1)
CEI-6G-SR/LR (1)
Concatenated (9)
Forward Error Correction (70)
LDPC (20)
Reed-Solomon (18)
Turbocode (6)
Viterbi (7)
Other (16)
Fibre Channel 16G (1)
Quadrature Amplitude Modulation (2)
Other (15)
EPON (1)
OTN (28)
PDH (3)
SONET / SDH (6)
SPI (12)
You must be registered with the D&R website to view the full search results, including:
Complete datasheets for
IP Core
products
Contact information for
IP Core
suppliers
Please
log in
here to your account.
New user ?
Signup here
.
146 IP
101
1.0
LTE / HSPA turbo decoder
TC1700 is a FEC receiver adressing LTE, LTE-A, WiMAX, HSPA/+, and legacy 3G standard. It cover Rate matching , HARQ combining and turbo decoding. The...
102
1.0
LTE / WiFi Viterbi decoder
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications. It covers optionally also WCDMA specifications....
103
1.0
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications. It support a decoded throughput up to 1...
104
1.0
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
105
1.0
DVB-RCS2 turbo decoder
TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications. Ideally suited fo systems requiring flexibility, short/medium ...
106
1.0
DVB-S2X LDPC/BCH Decoder
DVB-S2X is the next generation satellite transmission standard that extends its well-established predecessor DVB-S2. The new specification allows for ...
107
1.0
DVB-S2X Multi-Carrier Demodulator
The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel....
108
1.0
DVB-S2X Wideband Demodulator
The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 ...
109
1.0
DVB-S2X Wideband LDPC/ BCH Decoder
The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs...
110
1.0
DVB-S2X Wideband Modulator
The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...
111
0.0
G.9960 LDPC Decoder
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in th...
112
0.0
Fast Fourier Transform IP Core
The Creonic Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FF...
113
0.0
ECDSA sign engine
Elliptic curves form the foundation of cutting-edge public-key cryptography, serving as a crucial component for secure digital signatures and robust k...
114
0.0
ECDSA sign engine
When safety & security meet the best size/performance ratio… ECDSA IP Core Elliptic curves form the foundation of cutting-edge public-key cryptograph...
115
0.0
ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital Signature Algorithm ...
116
0.0
ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital Signature Algorithm ...
117
0.0
BCH Decoder IP
The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about p...
118
0.0
NCR Processor
NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...
119
0.0
CCSDS 8160/ 7136 Decoder and Encoder
...
120
0.0
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain h...
121
0.0
CCSDS SCCC Modulator/ Turbo Encoder
...
122
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
123
0.0
LDPC Decoder IS-GPS-800D IP
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
124
0.0
Reed Solomon
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...
125
0.0
Reed Solomon Decoder and Encoder FEC IP Core
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...
126
0.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
127
0.0
5G-NR LDPC Encoder
The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high th...
128
0.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
129
0.0
high-performance solution for elliptic curve cryptography
Our ECC IP Core represents a cutting-edge solution that brings the power of elliptic curve cryptography to your systems. Designed with versatility and...
130
0.0
WiMAX IEEE802.16e Transceiver IP Core
The transceiver is designed to be used together with an RF tuner and ADC/ DAC converters. The system has internal state machine to control the operat...
131
0.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....
132
0.0
Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...
133
0.0
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one it...
134
0.0
eMMC LDPC Encoder/Decoder
Mobiveil’s eMMC LDPC Encoder/Decoder is an advanced flash reliability solution engineered to maximize flash endurance and retention. Featuring industr...
135
0.0
Nonbinary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
136
0.0
Doppler Channel IP Core
The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...
137
0.0
ISDB-S3-LDPC-BCH Decoder IP
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...
138
0.0
LTE Turbo Decoder
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the interna...
139
0.0
DVB-C Demodulator IP Core
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine ...
140
0.0
DVB-C2 LDPC Decoder IP
The Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
141
0.0
DVB-C2 LDPC/ BCH Decoder IP Core
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes co...
142
0.0
DVB-S2-LDPC-BCH IP
The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broad...
143
0.0
DVB-S2X Modulator IP Core
IP core has two ways of forming the output spectrum: -Baseband (using odati and odatq), ifreq equal 0 -Intermediate frequency (using odati), ifreq not...
144
0.0
DVB-S2X-LDPC Decoder IP
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...
145
0.0
DVB-T2-LDPC-BCH IP
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC (Forward Error Correction) sub-system is needed. FEC...
146
0.0
DVB-T2/Lite LDPC Decoder IP
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...
|
Previous
|
3